1. Field of the Invention
The present invention relates generally to phase lock loops, and more particularly, but not exclusively, to methods and apparatus for a phase lock loop with a switch-capacitor loop filter.
2. Description of Background Art
As depicted in FIG. 1, a typical phase lock loop (PLL) based frequency synthesizer 100 includes a phase/frequency detector (PFD) 110, a charge pump (CP) circuit 120, a loop filter (LF) 130, and a voltage controlled oscillator (VCO) 140. The PFD 110 compares a reference clock and a feedback clock generated by the VCO to determine the phase difference. The PFD 110 outputs two logical signals, UP and DN signals to represent the phase difference between the two clocks. Each time a phase comparison is made, an UP signal pulse or a DN signal pulse is generated. If the reference clock is leading the feedback clock (in terms of clock phase), an UP pulse is generated. Otherwise, a DN pulse is generated. The width of the UP/DN pulse is proportional to the phase difference between the two clocks. The two logical signals UP and DN are converted into a current signal using the CP circuit 120. For example, the CP circuit 120 generates a positive (i.e. out-going) current pulse in response to a UP pulse, and generates a negative (i.e. in-coming) current pulse in response to a DN pulse. The output of the CP circuit 120 is connected to the LF 130, which typically includes a resistor in series with a capacitor to convert the output current from the CP circuit into a voltage. The output voltage from the LF circuit 130 is passed to the VCO 140 and used to control the frequency and accordingly the phase of the output clock generated by the VCO 140. The output clock of the VCO 140 is used as the feedback clock and provided to the PFD 110. The phase of the feedback clock is then compared with that of the reference clock by the PFD. A closed-loop control system is thus established to adjust the frequency/phase of the VCO 140 to track the frequency/phase of the reference clock. In steady state, the frequency of the output clock of the VCO 140 will be exactly the same as that of the reference clock.
An exemplary timing diagram shown in FIG. 2 illustrates a problem, referred to as “non-uniform sampling,” which exists in prior art phase lock loops (PLL) but is rarely discussed or addressed. When the reference clock leads the feedback clock, an UP pulse is generated; the UP pulse rises at the rising edge of the reference clock and falls at the rising edge of the feedback clock (see pulses 210 and 220). When the feedback clock leads the reference clock, a DN pulse is generated; the DN pulse rises at the rising edge of the feedback clock and falls at the rising edge of the reference clock (see pulses 230 and 240). The UP pulse always comes after the rising edge of the reference clock. On the other hand, the DN pulse always comes before the rising edge of the reference clock. The reference clock is usually a very stable clock, where the rising edges occur very regularly. Therefore, the timing and thus the effective sampling instant of a UP pulse differ from those of a DN pulse. The non-uniform sampling is a highly nonlinear phenomenon and results in increase of phase noise in the PLL output. This problem, however, is rarely discussed or addressed in prior art, because in steady state the frequency/phase of the VCO has been tracking well with that of the reference clock, the UP/DN pulses are thus very short, and therefore the non-uniform sampling problem is usually negligible. This problem, however, becomes an important source of performance degradation in an fractional-N frequency synthesizer.
A frequency synthesizer is an important application of PLL. A frequency synthesizer works in exactly the same manner as a general PLL shown in FIG. 1 and described above, except that we introduce a divide-by-N circuit (not shown in FIG. 1) into system such that the output clock of the VCO 140 is provided to the divide-by-N circuit to generate the feedback clock, instead of directly using the output clock of the VCO 140 as the feedback clock. For every N cycles of the VCO 140 output clock, the divide-by-N circuit generates a cycle of the feedback clock. The phase of the feedback clock, which is the output of the divide-by-N circuit, is then input into the PFD 110. The PFD 110 compares the feedback clock from the divide-by-N circuit with that of the reference clock. A closed-loop control system is thus established to adjust the frequency/phase of the VCO 140, and thus accordingly the frequency/phase of the feedback clock, to track the frequency/phase of the reference clock. In steady state, the frequency of the feedback clock will be the same as that of the reference clock, and therefore the frequency of the output clock of the VCO 140 will be N times of that of the reference clock.
The divide-by-N circuit for frequency synthesizer can be conveniently implemented using a divide-by-N counter if N is an integer. If N is a fractional number, a straight implementation using a counter with a fixed divisor value will not work, since the divisor value of a counter needs to be an integer. To implement a fractional N, say N=Nint+α, where Nint is an integer and α is a fractional number between 0 and 1, the divisor value for the counter is dynamically shuffled. For example, the divisor value is dynamically shuffled between Nint and (Nint+1); the effective divisor value will be N=Nint+α as long as the probability of having the divisor value of (Nint+1) is α (and the probability of having Nint is (1−α)). In some prior art devices, a delta-sigma modulator is often used to dynamically shuffle the divisor value.
Dynamically shuffling the divisor value effectively achieves a fractional N division. However, this shuffling causes elongated UP and DN pulses, which result in elongated current pulses from the CP circuit and consequently cause excessive phase changes to the output clock of the VCO. As a result, the output clock of the VCO contains excessive phase noises albeit the mean frequency is correctly N times that of the reference clock. The excessive phase noise problem, fortunately, can be alleviated using the delta-sigma modulator. Using the delta-sigma modulator to shuffle the divisor value, we spectrally shape the excessive phase noise caused by the shuffling. Consequently, the phase noise mainly consists of high frequency components and can be effectively attenuated by the loop filter. However, the aforementioned non-uniform sampling problem becomes very significant due to elongated UP/DN pulses. The nonlinearity due to non-uniform sampling causes an inter-modulation among the high-frequency phase noises. As a result, there will be a significant increase in low-frequency phase noises that cannot be filtered by the loop filter.
What is needed is a method to alleviate the non-uniform sampling problem, in particular for fractional-N synthesizer applications.